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DDU8C3-5050 spec: Total delay 50 +/-2.5 ns, 5-TAP, 3.3V CMOS-interfaced fixed delay line
Ähnliche DDU8C3-5050
- DDU8C-5050
- Total delay 50 +/-2.5 ns, 5-TAP, HCMOS-interfaced fixed delay line
- DDU8C-5050A1
- Total delay 50 +/-2.5 ns, 5-TAP, HCMOS-interfaced fixed delay line
- DDU8C-5050B1
- Total delay 50 +/-2.5 ns, 5-TAP, HCMOS-interfaced fixed delay line
- DDU8C-5050M
- Total delay 50 +/-2.5 ns, 5-TAP, HCMOS-interfaced fixed delay line
- DDU8C-5050MD1
- Total delay 50 +/-2.5 ns, 5-TAP, HCMOS-interfaced fixed delay line
- DDU8C-5050MD1
- Total delay 50 +/-2.5 ns, 5-TAP, HCMOS-interfaced fixed delay line
- DDU8C-5050MD4
- Total delay 50 +/-2.5 ns, 5-TAP, HCMOS-interfaced fixed delay line
- DDU8C-5050MD4
- Total delay 50 +/-2.5 ns, 5-TAP, HCMOS-interfaced fixed delay line
DDU8C3-5050 Datenblatt und Spezifikationen
Hersteller : Data Delay Devices
Verpacken : DIP
Pins : 8
Temperatur : Min -40 °C | Max 85 °C
Größe : 49 KB
Application : Total delay 50 +/-2.5 ns, 5-TAP, 3.3V CMOS-interfaced fixed delay line
DDU8C3-5050 PDF-Download