Path:OKDatasheet > Halbleiter Datenblatt > Data Delay Devices Datenblatt > PDU53-100
PDU53-100 spec: Delay 100 +/-50 ns, 3-BIT, ECL-interfaced programmable delay line
Ähnliche PDU53-100
- PDU53-100
- Delay 100 +/-50 ns, 3-BIT, ECL-interfaced programmable delay line
- PDU53-1000
- Delay 1000 +/-200 ns, 3-BIT, ECL-interfaced programmable delay line
- PDU53-1000C3
- Delay 1000 +/-200 ns, 3-BIT, ECL-interfaced programmable delay line
- PDU53-1000M
- Delay 1000 +/-200 ns, 3-BIT, ECL-interfaced programmable delay line
- PDU53-1000MC3
- Delay 1000 +/-200 ns, 3-BIT, ECL-interfaced programmable delay line
- PDU53-100C3
- Delay 100 +/-50 ns, 3-BIT, ECL-interfaced programmable delay line
- PDU53-100C3
- Delay 100 +/-50 ns, 3-BIT, ECL-interfaced programmable delay line
- PDU53-100M
- Delay 100 +/-50 ns, 3-BIT, ECL-interfaced programmable delay line
PDU53-100 Datenblatt und Spezifikationen
Hersteller : Data Delay Devices
Verpacken : DIP
Pins : 16
Temperatur : Min 0 °C | Max 70 °C
Größe : 43 KB
Application : Delay 100 +/-50 ns, 3-BIT, ECL-interfaced programmable delay line
PDU53-100 PDF-Download