Path:OKDatasheet > Halbleiter Datenblatt > Lattice Datenblatt > MACH210A-7JC
MACH210A-7JC spec: High-density EE CMOS programmable logic, 64 macrocells, 32 outputs, 38 Inputs, 64 flip-flops; 2 clock choices, 7ns, input pull-up resistors
Ähnliche MACH210A-7JC
- MACH110-12JC
- High-density EE CMOS programmable logic, 32 macrocells, 38 Inputs, 12ns
- MACH110-14JI
- High-density EE CMOS programmable logic, 32 macrocells, 38 Inputs, 14ns
- MACH110-15JC
- High-density EE CMOS programmable logic, 32 macrocells, 38 Inputs, 15ns
- MACH110-18JI
- High-density EE CMOS programmable logic, 32 macrocells, 38 Inputs, 18ns
- MACH110-20JC
- High-density EE CMOS programmable logic, 32 macrocells, 38 Inputs, 20ns
- MACH110-24JI
- High-density EE CMOS programmable logic, 32 macrocells, 38 Inputs, 24ns
- MACH111-10JC
- High-performance EE CMOS programmable logic, 32 macrocells, 32 I/Os, 10ns
- MACH111-10JI
- High-performance EE CMOS programmable logic,32 macrocells, 32 I/Os, 10ns
MACH210A-7JC Datenblatt und Spezifikationen
Hersteller : Lattice
Verpacken : PLCC
Pins : 44
Temperatur : Min 0 °C | Max 70 °C
Größe : 381 KB
Application : High-density EE CMOS programmable logic, 64 macrocells, 32 outputs, 38 Inputs, 64 flip-flops; 2 clock choices, 7ns, input pull-up resistors
MACH210A-7JC PDF-Download